Conventional semiconductor memory devices utilizing multiple array memory structures, such as synchronous dynamic random access memory (SDRAM) devices employing bank structures, often employ pipelining-type operations among different banks to enhance performance, but generally do not support pipelining-type operations within a given bank. This “limitation” is due primarily to the use of global timing signals which require that transactions to a given bank be successive in nature, such that a transaction with a first memory array of the given bank be completed before a transaction with a second memory array of the given bank can be initiated.
FIG. 1 is a block diagram illustrating generally an example bank structure of a conventional multiple array memory system 30. As illustrated, a plurality of memory arrays, indicated as memory arrays 32m to 32n, together form a memory array bank 34. Memory system 30 further includes a bank controller 36 that provides global array and row address signals and global timing signals, such as row address signals (RAS) and wordline on signals, via a row bus 38, and global column address and timing signals, such as column address signals (CAS), via a column bus 40.
Each memory array of memory array bank 34 is coupled to row bus 38 via a corresponding row control block, indicated as 42m to 42n, and to column bus 40 via a column redundancy and control block 44 and a column decoder 46. Each memory array is further coupled to a data input/output (I/O) block 48 via global data buses 50a and 50b. 
To access a memory array within memory array bank 34, such as memory array 32m, bank controller 36 first “activates” array 32m by providing the proper array address via row bus 38. Once array 32m is activated, bank controller 36 provides via row bus 38 a subsequent series of global timing signals to carry out the desired access operation, such as a word-line selection (WL) signal, a bit-line sense-amp (BL S/A) control signal, etc. The subsequent series of timing signals are provided to each memory array 32m to 32n of bank 34 via corresponding row control blocks 42m to 42n; however, only the activated array, in this case array 32m, responds to the subsequent series of timing signals.
Because of the global nature of the timing signals, the access operation of array 32m must be complete before an access operation to another array, such as array 32n, can be initiated. Otherwise, if array 32n is activated prior to completion of the access operation of array 32m, both arrays would respond to the subsequent global timing signals and result in an erroneous multiple array operation due to wrongful timing signal inputs.
FIG. 2 is an exemplary timing diagram 60 illustrating generally transactions of a conventional multiple array memory system, such as memory system 30 of FIG. 1. In the illustrative example, a system clock is illustrated at 62 and command row 64 illustrates system commands in SDRAM form.
Bank controller 36 first issues a “bank activate” command 68. As illustrated, bank activate command 68 (Act_Bk<a>) activates memory array bank “a.” Memory array <m> 32m within memory array bank <a> is then activated for a row operation as indicated by row operation period 68. An operation to a selected row of memory array <m> 32m, such as a read or a write operation, is then initiated as indicated at 70. Upon completion of the read or write operation 70, a precharge command 72 for memory array bank <a> is initiated. Subsequently, memory array <m> 32m is precharged, as indicated by precharge period 74. The total cycle time tRC for the transaction to a row within memory array <m> 32m of memory array bank <a>, including row operation period 68 and precharge period 74, is indicated at 76.
As indicated at 78, a next bank activate command Act_Bk<a> cannot be issued to memory array bank <a> until after the total cycle time tRC 76 has elapsed. After this time, another transaction can take place within memory array bank <a>, such as a row operation to memory array <n> as indicated at 80. Command row 82 illustrates commands for a similar operation in an SRAM-like (Static Random Access Memory) form.
As illustrated above, because of the global nature of the timing signals, a transaction to first memory array of a bank must be completed before a transaction to another memory array of the bank is initiated to avoid an ambiguous output situation where more than one memory array in a bank responds to a same sequence of timing signals. As a result, the bandwidth of a conventional multiple array memory bank structure is restricted by the global nature of the memory system timing signals.